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Formal Verification jobs at Cadence Design Systems

Explore 17 current openings. Compare roles, companies, locations, and work options, then open any job to view the full details.

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Current openings

Showing 20 jobs

  1. Lead Verification Engineer

    Cadence Design Systems

    Lead Verification Engineer at Cadence Design Systems drives AI-driven pre-silicon verification. Leveraging formal verification, UVM, and machine learning, the role architects next‑generation verification methodologies. …

    NOIDA, IndiaOn-siteFull-time
    Active

  2. Principal Verification Engineer

    Cadence Design Systems

    Cadence seeks a Principal Verification Engineer to lead validation of Palladium emulation technologies, including UPF. The role involves verifying new features, managing regression suites, reviewing functional …

    Noida, IndiaOn-siteFull-time
    Active

  3. Lead Product Engineer

    Cadence Design Systems

    Cadence Design Systems seeks a Lead Product Engineer to drive development of UCIe verification IP. The role requires deep expertise in UCIe domain, SystemVerilog, and UVM methodology, and a proven track record of …

    Noida, IndiaOn-siteFull-time
    Active

  4. Sr Principal Design Engineer

    Cadence Design Systems

    Cadence is a leader in electronic design, building software, hardware, IP for chips to systems. This role is a Design Verification engineer for IP development team, focusing on Serial and Interface Design IPs (PCIe, …

    NOIDA, IndiaOn-siteFull-time
    Active

  5. Sr Principal Verification Engineer

    Cadence Design Systems

    Cadence seeks a Sr Principal Verification Engineer to lead pre‑silicon verification using AI. The role blends formal verification, UVM, and ML to accelerate design validation. Candidates will architect AI‑enhanced …

    BANGALORE, IndiaOn-siteFull-time
    Active

  6. Software Engineer

    Cadence Design Systems

    Cadence Design Systems’ Formal Verification team in NOIDA builds Assertion Based Verification IPs for industry standard bus protocols. The role focuses on developing Verilog design models, SystemVerilog assertions, and …

    NOIDA,IndiaOn-siteFull-time
    Active

  7. Lead Verification Engineer

    Cadence Design Systems

    Cadence Design Systems seeks a Lead Verification Engineer to pioneer AI-driven pre‑silicon verification. The role blends formal and UVM verification expertise with machine‑learning techniques, leveraging LLMs and …

    Bangalore, IndiaOn-siteFull-time
    Active

  8. Lead Software Engineer

    Cadence Design Systems

    Cadence seeks a Lead Software Engineer in Ahmedabad to design and develop verification IP (VIP) using C/C++. The role requires strong expertise in SystemVerilog/UVM verification, digital electronics fundamentals, and …

    Ahmedabad, IndiaOn-siteFull-time
    Active

  9. Principal Design Engineer

    Cadence Design Systems

    Cadence seeks a Principal Design Engineer for its IP Group in Bangalore. The role focuses on verification of serial and interface IPs (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C) using UVM …

    BANGALORE, IndiaOn-siteFull-time
    Active

  10. Lead Software Engineer

    Cadence Design Systems

    Cadence Formal Verification team builds cutting-edge verification tools for electronic design, focusing on JasperGold applications. The Lead Software Engineer drives formal verification features, integrates machine …

    NOIDA,IndiaOn-siteFull-time
    Active

  11. Principal Software Engineer

    Cadence Design Systems

    Cadence seeks a Principal Software Engineer to develop and verify VIP IP tools. The role requires 8+ years of domain experience, proficiency in SV/UVM functional verification, Python scripting, and memory verification …

    Bangalore, IndiaOn-siteFull-time
    Active

  12. Sr Principal Verification Engineer

    Cadence Design Systems

    Senior Verification Engineer with 12-15+ years in pre-silicon ASIC verification, specializing in formal and UVM methodologies. Expert in debugging verification failures using waveform viewers and simulation tools, and …

    NOIDA, IndiaOn-siteFull-time
    Active

  13. Principal Design Engineer

    Cadence Design Systems

    Principal Design Engineer at Cadence Design Systems leading verification of Serial and Interface IPs, developing UVM testbenches, performing formal verification and emulation qualification, creating verification …

    BANGALORE, IndiaOn-siteFull-time
    Active

  14. Principal Design Engineer

    Cadence Design Systems

    Cadence Design Systems seeks a Principal Design Engineer to lead verification of Serial and Interface IPs such as PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI. The role develops UVM testbenches, performs …

    BANGALORE, IndiaOn-siteFull-time
    Active

  15. Design Engineering Architect

    Cadence Design Systems

    Cadence IP Group designs and verifies high‑performance interface IPs. The Design Engineering Architect leads verification strategy, builds UVM testbenches, and may conduct formal verification and emulation qualification …

    Bangalore,India,IndiaOn-siteFull-time
    Active

  16. Principal Education Application Engineer

    Cadence Design Systems

    Cadence’s Education & Training team builds high‑impact learning content for verification engineers. The role authorizes and delivers lectures, labs, and demos on UVM, hardware acceleration, and emulation, supporting …

    Bangalore,IndiaOn-siteFull-time
    Active

  17. Lead Design Engineer

    Cadence Design Systems

    Cadence is a leader in electronic design, building software, hardware, and IP that turn concepts into reality. The Lead Design Engineer will develop and verify high‑level verification environments using SystemVerilog, …

    Bangalore, IndiaOn-siteFull-time
    Active

  18. Lead Design Engineer

    Cadence Design Systems

    Cadence Design Systems’ Lead Design Engineer drives the DV architecture for next‑generation Tensilica CPUs, defining scalable verification methodologies and leading UVM environment development. The role architects …

    Pune,IN,IndiaFull-time
    Active

  19. Principal Design Engineer

    Cadence Design Systems

    Principal Design Engineer at Cadence leads DV architecture for Tensilica CPUs, defining scalable verification strategies across processor variants. Designs simulation testbenches in C/C++/RTL, builds reusable UVM …

    Pune, IndiaOn-siteFull-time
    Active

  20. Principal Software Engineer (Verification of VIP using Verilog/SV/UVM)

    Cadence Design Systems

    Cadence Design Systems seeks a Principal Software Engineer to lead verification of VIP components using Verilog, SystemVerilog, and UVM in Ahmedabad. The role involves managing multiple VIPs, leading a small team, and …

    Ahmedabad, IndiaOn-siteFull-time
    Active

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