Clock Tree Synthesis jobs
Explore 14 current openings. Compare roles, companies, locations, and work options, then open any job to view the full details.
Current openings
Showing 20 jobsSenior CAD Engineer - SOC Clocks Design Methodology
2100 NVIDIA USAThe NVIDIA Clocks Team seeks a Senior CAD Engineer to lead clocking and reset logic design for SOCs across consumer graphics, autonomous vehicles, and AI. Responsibilities include owning infrastructure for clocking …
Bengaluru, IndiaHybridFull-timeActivePhysical Design Engineer
100 Intel CorporationPhysical Design Engineer responsible for end‑to‑end physical implementation of custom IP and SoC designs from RTL to GDS. Executes synthesis, place‑and‑route, clock‑tree synthesis, floor planning, static timing …
Bangalore, IndiaOn-siteFull-timeActivePrincipal Engineer - SOC Clocking
IntelLead the architecture, design, and integration of SoC‑wide clocking networks including clock generation (PLLs, DLLs), distribution, gating, and domain crossing strategies. Define and optimize power‑performance‑area …
Bangalore, IndiaOn-siteFull-timeActivePhysical Design Engineer
IntelThe Physical Design Engineer will implement custom IP and SoC designs from RTL to GDS, ensuring readiness for manufacturing. Responsibilities include synthesis, place and route, clock tree synthesis, and various …
India, BangaloreOn-siteFull timeActiveSoC Physical Design Clocking Engineer
IntelSoC Clocking team at Intel builds next‑generation server SoC clock architectures. The engineer designs, simulates, and signs off on clock distribution, PLL/DLL IPs, and system‑level clocking flows, collaborating with …
Bangalore,IndiaFull-timeActivePhysical Design Engineer
IntelCentral Engineering Group (CEG) at Intel builds scalable engineering solutions for custom ASIC and foundry enablement. The Physical Design Engineer implements custom IP and SoC designs from RTL to GDS, handling …
Bangalore,India,IndiaOn-siteFull-timeActiveSoC Physical Design Clocking Engineer
IntelSoC Clocking team at Intel’s Data Center Group builds next‑generation server SoC clock architectures. The engineer designs, simulates, and signs off on clock distribution, PLL/DLL IPs, and system‑level clocking flows, …
Bangalore,IndiaHybridFull-timeActivePhysical Design Engineer
AlteraPhysical Design Engineer at Altera Semiconductor Technology India Pvt. Ltd. Works on the physical design implementation of custom IP and SoC designs from RTL to GDS, performing synthesis, place and route, clock tree …
Regus, Madhapur, IndiaOn-siteFull-timeActiveSoC Physical Design Clocking Engineer
IntelSenior engineer with over a decade of experience in SoC clock architecture and implementation, specializing in clock distribution, PLL/DLL design, and jitter analysis. Proven track record in developing scalable clocking …
Bangalore, IndiaHybridFull-timeActivePhysical Design Engineer
IntelIntel Central Engineering Group (CEG) builds scalable engineering solutions for custom ASIC and foundry enablement. The Physical Design Engineer implements physical design flow from RTL to GDS, performing synthesis, …
Bangalore,IndiaHybridFull-timeActivePhysical Design Engineer
100 Intel CorporationPhysical Design Engineer responsible for end-to-end physical design of custom IP and SoC from RTL to GDS, including synthesis, place/route, clock tree synthesis, floor planning, static timing analysis, power …
Bangalore, IndiaOn-siteFull-timeActiveTechnical Director -SoC architecture (boot, power management, clock & reset, security)
Silicon LaboratoriesSilicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most …
Hyderabad, IndiaOn-siteFull-timeActivePrincipal Engineer
100 Intel CorporationPrincipal Engineer – SOC Clocking at Intel leads the design and integration of SoC‑wide clocking networks, optimizing power‑performance‑area trade‑offs and ensuring robust silicon correlation. Responsibilities include …
Bangalore, IndiaOn-siteFull-timeActiveSenior Physical Design Engineer
IntelIntel Central Engineering Group’s Physical Design team builds cutting‑edge custom IP and SoC designs for Intel products and custom ASIC customers. The role translates RTL to GDS, leading synthesis, place‑and‑route, …
Bangalore,IndiaHybridFull-timeActiveASIC Verification Engineer
NvidiaSenior ASIC Verification Engineer for NVIDIA Clocks Team, responsible for end-to-end validation of clocking structures in Tegra automotive and datacenter products. Develop test plans, automation, coverage metrics, …
Bengaluru,IndiaHybridFull-timeActiveSenior Physical Design Engineer
IntelSenior Physical Design Engineer on Intel’s Central Engineering Group (CEG) team, driving the end‑to‑end physical design flow for custom IP and SoC products. The role leads a small team through synthesis, floor planning, …
Bangalore,IndiaFull-timeActiveASIC Verification Engineer
NvidiaSystem ASIC Verification team at NVIDIA drives high-quality verification of system‑level IP across unit, subsystem, and SoC levels. The engineer develops test plans, builds reusable SystemVerilog/UVM testbenches, and …
Bengaluru,IN,IndiaHybridFull-timeActivePhysical Design Engineer
AlteraPhysical Design Engineering team at Altera focuses on turning custom IP and SoC RTL into manufacturable GDS databases. The engineer drives the full physical design flow—synthesis, floorplanning, place & route, clock …
Regus, Madhapur,IndiaOn-siteFull-timeActiveDigital Physical Design Engineer
NXP SemiconductorsWe are seeking a skilled and enthusiastic Digital Physical Design Engineer (G2) to contribute to the physical implementation of complex digital integrated circuits. This role involves working on various stages of the …
Pune, IndiaOn-siteFull-timeActiveAssociate - Evidence Synthesis
SanofiJob title: Associate – Evidence Synthesis Hiring Manager: Head/Group Lead//Team Lead Location: Hyderabad % of travel expected: Travel required as per business need Job type: Permanent and Full time About the job Our …
Hyderabad, IndiaOn-siteFull-timeActive