Floorplanning jobs

SOC Floorplan Execution Lead

This role leads the floorplan and physical design of ASIC-based SoCs for Intel’s graphics and AI products. The candidate will manage end‑to‑end floor‑planning, clocking, synthesis, place‑and‑route, static timing …

Senior GPU Floorplan Design Engineer

GPU Architecture Team at NVIDIA designs next‑generation GPUs. The Senior GPU Floorplan Design Engineer crafts and optimizes early chip floorplans, drives area review processes, and resolves timing and routing congestion …

Staff/Senior Staff Physical Design Floorplan & PDN Lead

EnCharge AI, a leader in advanced AI hardware and software for edge-to-cloud computing, builds next‑generation in‑memory computing platforms. The Staff/Senior Staff Physical Design Floorplan & PDN Lead architects …

Sr Principal Design Engineer

NXP Semiconductors – Digital Physical Design team. Designs physical implementation of IP, subsystem or IC from RTL synthesis through GDS, handling floorplanning, routing, timing convergence and verification. Works in …

Principal Engineer, ASIC Development Engineering, Physical Design, PNR, Floorplan

Principal VLSI Design Engineer

VLSI Design Engineering team at SanDisk focuses on advanced memory chip development. The Principal VLSI Design Engineer drives full chip integration, power distribution and floorplanning, and leads cross‑functional …

Analog Layout Design Engineer

Designs complex analog layout circuits, verifies design rules, ESD, IR, reliability checks, floorplans, power grid, bumps, micro‑floor and signal planning, shielding, matching, area, power, performance optimization. …

Sr Principal Engineer

Digital Physical Design team at NXP Semiconductors focuses on implementing IP, subsystems, and IC designs from RTL synthesis through GDS. The Sr Principal Engineer leads floorplanning, routing, timing convergence, and …

Member of Technical Staff Analog Engineering

Memory Interface Chip (MIC) group at Rambus develops cutting‑edge memory interface solutions. The MTS designs and verifies high‑speed analog circuits, creates floorplans, simulates behavior, and collaborates …

Senior Physical Design Engineer

VLSI Design team at NXP Semiconductors builds advanced SoC/IP blocks for high‑performance, low‑power applications. The Senior Physical Design Engineer drives block‑level implementation from floorplanning through …

NoC (RTL) Design - PE/Director

Qualcomm's NoC/Interconnect core team designs next‑generation SoC interconnects for smartphones and emerging devices. The Director leads specification, RTL design, micro‑architecture and cross‑team integration, driving …

Staff Engineer, RTL Design

Hardware Engineering team at Qualcomm focuses on designing complex SoCs. The Staff Engineer, RTL Design, leads RTL coding, micro-architecture, and constraint development, collaborates with verification, validation, and …

Physical Design Engineer

ASIC R&D team at Syntiant drives cutting‑edge edge‑AI silicon. The Physical Design Engineer leads the end‑to‑end RTL‑to‑GDSII flow, delivering best‑in‑class performance, power and area for next‑generation ASICs while …

Implementation Engineer

Technology Department at Tata Consultancy Services focuses on delivering end‑to‑end VLSI design solutions. The Implementation Engineer executes RTL to GDSII physical design flow, handling floorplanning, power planning, …

Senior PD CAD Engineer

Physical Design (PD) team at Qualcomm India focuses on chip floorplanning and place-and-route to optimize performance, power, and area. The Senior PD CAD Engineer executes PD at block/SoC level, improves PPA, supports …

Staff Engineer, ASIC Physical Design

Enterprise SSD Group at Micron Technology designs processors, controller architectures and ASICs for high‑performance storage. The Staff Engineer leads ASIC physical design, handling floorplanning, placement, CTS, …

PE Analog Engineer

Memory Interface Chip Design team at Rambus develops high‑performance mixed‑signal products to accelerate data movement. The PE Analog Engineer leads analog/mixed‑signal circuit design, creates models, collaborates on …

Senior Physical Design Engineer

Semiconductor Design Team at Microsoft builds cutting-edge ASICs for next‑generation products. The Senior Physical Design Engineer leads block‑to‑chip level physical implementation, including floorplanning, synthesis, …

Senior Digital Backend Engineer

Digital Physical Design team at NXP Semiconductors builds and optimizes the physical implementation of IP, subsystems, and IC designs. The Senior Digital Backend Engineer leads RTL synthesis through GDS implementation, …