Low‑Power Design jobs

ASIC Engineer, Implementation, Low-Power Design

Meta Silicon Engineering team builds custom silicon powering Meta's AI and data center workloads. The ASIC Engineer, Implementation focuses on low-power design, developing power modeling flows in Python/C++, driving …

Senior Engineer [Microcontroller RTOS]

Senior Engineer with expertise in C coding and RTOS (Micrium OS, FreeRTOS). Skilled in SiLabs, STMicro, NXP Cortex M3/M4/M0+ microcontrollers, low‑power optimization, and peripheral interfaces (I2C, SDIO, UART, SPI, …

Staff Director, Low Power AI HW Product Management

Operations Group Product Management at Qualcomm drives low-power AI and ambient compute platforms. The role defines and executes product strategy for the Low Power AI subsystem and microNPU, collaborating across …

Technical Consultant

Lead technical consultant delivering enterprise‑scale Power Platform and full‑stack solutions, integrating AI/LLM, Azure, and O365. Drive design, architecture, coding standards, and Agile delivery. Mentor teams, adopt …

Principal Digital Design Engineering

Analog Devices seeks a Principal Digital Design Engineer to lead low‑power methodology and circuit design in advanced technology nodes. Responsibilities include writing architecture specifications, designing RTL and UPF …

Principal Engineer Design

Design Engineering team at Infineon Technologies drives low‑power methodology for ASICs. The role defines UPF flows, creates early power estimation workflows, and partners with power architecture, verification and EDA …

Verification Engineer, Low Power

NVIDIA is seeking a Verification Engineer, Low Power to join its Bengaluru team. The role focuses on structural and functional verification of low‑power features across NVIDIA’s chip family. Responsibilities include …

Low Power Design Engineer Sr Lead

Product Engineer II, Low Power

Cadence Design Systems' Verification team builds advanced low‑power verification flows for Xcelium. The Product Engineer II creates product requirements, automates tool flows, and collaborates with R&D and customers to …

Power Architecture Engineer

NVIDIA Power Architecture Engineer role in Bengaluru. Join NVIDIA Power Architecture Group to design, analyze, and verify power features across ASICs, silicon, and system-level solutions. Responsibilities include power …

Low Power ML Accelerator Software Senior Engineer

Multimedia AI Software Group at Qualcomm develops low power AI accelerator software for Snapdragon platforms. The Senior Engineer designs, implements, and integrates ML frameworks and kernels for Qualcomm's low‑power ML …

Lead Hardware Engineer

Lead Hardware Engineer at Cadence Design Systems. Responsible for synthesis, PnR, SOC design, methodology improvement, floor planning, placement, routing, low power synthesis, scripting, verification. Works with RTL, …

Senior Engineer I - Design

Microchip Technology seeks a Senior Engineer I – Design to lead the development of next‑generation low‑power wireless SoCs. The role involves full SOC design from concept to tape‑out, including RTL coding, synthesis, …

Verification Engineer, Low Power

NVIDIA is a leading technology company known for GPU innovation and AI research. This role focuses on structural and functional verification of low‑power features across NVIDIA’s chip family. Responsibilities include …

Senior Engineer I

Microchip’s DSPIC Business Unit seeks a Physical Design Engineer to drive microcontroller and SOC designs, delivering next‑gen low‑power mixed‑signal solutions. Responsibilities include implementing complex designs with …

Low Power Machine Learning Software Senior Engineer

Multimedia AI Software Group at Qualcomm develops low‑power machine‑learning accelerator software for Snapdragon platforms. The Senior Engineer designs, implements, and integrates ML frameworks and kernels for the …

Staff Engineer, ASIC STA

Enterprise SSD Group’s ASIC design team at Micron transforms memory controllers into high‑performance, low‑power silicon. The role drives block‑level floorplanning, synthesis, STA, and low‑power verification to achieve …

ASIC RTL Design Engineer III, Silicon

Platforms and Devices team at Google builds custom silicon that powers direct‑to‑consumer products. As an ASIC RTL Design Engineer III, you design micro‑architecture for mobile SOC subsystems, integrate first‑party and …

Low Power Multimedia Systems Engineer

Multimedia Architecture Power Team at Qualcomm builds embedded imaging solutions for Snapdragon chipsets powering Mobile, Automotive, IoT, and XR devices. The engineer defines power‑efficient system architectures for …